Global Memory and Storage Capacity Buildout: Who Is Building What, Where, and When

1. Executive Summary

The global memory and storage capacity buildout is no longer a single-cycle story. It is now a layered supply-stack story in which front-end wafer capacity, reserved cleanroom shells, advanced packaging, module assembly, and technology-node migration all determine the real bit supply that reaches customers. The most important near-term additions are concentrated in HBM-linked DRAM and advanced packaging, while broad-based conventional DRAM and NAND relief remains skewed toward 2027, 2028, and later. Reuters reported in Jan 2026 that new conventional memory factories were not expected online until 2027 or 2028, and Micron stated in FY2Q26 materials that both DRAM and NAND bit demand in calendar 2026 are supply-constrained and that conditions are likely to remain tight beyond 2026.

HBM remains the tightest part of the system because incremental HBM supply requires much more than incremental DRAM wafer starts. It requires front-end DRAM output, known-good-die yield, logic base die, TSV-related stacking flow, substrate/interposer availability, advanced packaging throughput, and final test. Micron explicitly tied tightness beyond 2026 to higher HBM trade ratios, cleanroom additions, and node migrations that reduce DRAM bits per wafer, and also noted that some suppliers are redirecting cleanroom space from NAND to DRAM. That combination means AI-memory investment can tighten commodity DRAM and indirectly constrain NAND even while headline capex is rising.

Capital formation is also changing. Korea’s leaders are funding most expansion from internal resources, but with increasing policy support for overseas projects. U.S. and Japan projects are materially subsidy-backed. Taiwan is beginning to use strategic equity placements tied to offtake. China remains more dependent on state-backed IPOs, local capital vehicles, and less transparent ecosystem financing. The highest-confidence ramps are therefore the projects where 3 elements are already visible at the same time: a funded physical shell or tool plan, a disclosed schedule, and a customer path or qualification signal.

2. Samsung — HBM and DRAM

Samsung’s disclosed memory expansion is centered on Pyeongtaek infrastructure, back-end HBM capability, and a 2026 HBM4 ramp rather than a newly quantified greenfield commodity-memory fab. Samsung’s annual disclosures state that infrastructure buildout continued at Pyeongtaek to secure cleanrooms for mid- to long-term demand, while back-end investment was increased to expand HBM and high-density module production capability. Reuters then reported in Feb 2026 that Samsung had started shipping HBM4 to customers and planned HBM4E samples in 2H26. Exact incremental wafer-start capacity or package-unit output for Pyeongtaek was not publicly disclosed in the reviewed materials, which means the economically relevant data point is not a headline wafers-per-month figure but the combination of reserved cleanroom space, back-end expansion, and customer qualification timing.

The clearest identified Samsung HBM customer is AMD. Samsung and AMD announced on Mar 18, 2026 that Samsung would be AMD’s primary HBM4 supplier for the Instinct MI455X, while also supplying advanced DDR5 for 6th Gen EPYC Venice and AMD Helios systems. Samsung stated that its HBM4 is built on 1c DRAM and a 4nm logic base die and can deliver up to 13 Gbps and 3.3 TB/s. At the corporate level, Samsung said 2025 total investment reached 90.4 trillion won, including 52.7 trillion won of capex, and that 2026 investment would exceed 110 trillion won across R&D and facilities. The analytical conclusion is that Samsung is preserving large cleanroom optionality for AI memory while using customer commitments to determine the pace at which that capacity is actually tooled and qualified.

Samsung’s commercial posture also signals that tightness is not ending quickly. Reuters reported in Mar 2026 that Samsung’s co-CEO said the memory shortage was continuing to drive demand and that the company was seeking 3-year to 5-year supply contracts, while a Samsung executive said in Feb 2026 that strong demand for memory chips was expected through 2027. That is a meaningful market structure signal. When a top-2 supplier is pushing multiyear contracts while simultaneously reserving cleanroom space rather than disclosing large immediate commodity capacity, it implies both confidence in sustained AI memory demand and caution about oversupplying standard DRAM or NAND too early.

Samsung’s P5 facility at Pyeongtaek is expected online by 2028. Samsung is also ending MLC NAND production by June 2026, contributing to an estimated 40% drop in global MLC capacity. Samsung’s 2026 capex will exceed 40 trillion won, with approximately 90% allocated to DRAM and only ~10% to NAND — underscoring the structural underinvestment in conventional NAND that is driving flash prices higher.

3. SK Hynix — HBM and DRAM

SK Hynix has the most clearly staged HBM-linked physical expansion program. The 1st leg is M15X in Cheongju, announced as a next-generation DRAM production base for future DRAM including HBM. The company disclosed about 5.3 trillion won for fab construction, stated that long-term total investment would exceed 20 trillion won, and targeted completion in Nov 2025. Reuters later reported that wafers started going into M15X in Feb 2026 for HBM-related production. At full utilization across both cleanrooms, M15X can add up to 90,000 12-inch wafers per month of DRAM capacity, with mass-produced products expected from the first cleanroom as early as 1H26. Exact wafers-per-month were not officially disclosed, but M15X is strategically important because it is a real 2026 front-end addition rather than a distant shell.

The 2nd leg is the 1st Yongin fab, which extends SK Hynix’s medium-term DRAM and HBM runway. In Feb 2026 SK Hynix said it would invest 21.6 trillion won in a new Yongin facility by Dec 2030, lifting total investment for the 1st fab to about 31 trillion won including prior spending. The company accelerated the opening of the 1st cleanroom from May 2027 to Feb 2027 and disclosed that the 1st fab would include 2 building shells and 6 cleanrooms. Importantly, the 21.6 trillion won facility figure excludes equipment installation, so eventual all-in capital intensity will be materially higher than the disclosed civil and facility spend. The practical implication is that Yongin is not a 2026 supply event, but it is the most important 2027–2030 DRAM platform under construction outside Micron’s U.S. roadmap.

The 3rd leg is advanced packaging. Reuters reported in Jan 2026 that SK Hynix would spend 19 trillion won on an advanced packaging plant in South Korea, with construction beginning in Apr 2026 and completion targeted for end-2027. The 4th leg is the U.S. advanced packaging and R&D facility in West Lafayette, Indiana, where SK Hynix plans to invest about $3.87 billion to mass-produce next-generation HBM beginning in 2H28. U.S. support materially de-risks that program: the U.S. Commerce Department said the project is eligible for up to $458 million in direct funding and up to $500 million in loans. Reuters also reported that a potential U.S. listing could raise 10 trillion won to 15 trillion won for advanced memory investment, although that financing route was not finalized. This is a uniquely complete expansion stack: 2026 front-end wafers at M15X, 2026–2027 domestic packaging construction, 2027 Yongin cleanroom availability, and 2028 U.S. HBM packaging output.

An additional signal of how serious SK Hynix is about next-generation DRAM and HBM is tool ordering. Reuters reported in Mar 2026 that SK Hynix placed an 11.95 trillion won order — the largest ever publicly disclosed by a single ASML customer — for ASML EUV tools through Dec 2027 for next-generation memory production. While the company did not publicly allocate those tools by specific fab, the scale is consistent with a multiyear build across M15X, Yongin, and related leading-edge DRAM nodes. Reuters also reported in Jan 2026 that SK Hynix’s 2026 HBM output was effectively sold out, with AI customers including Nvidia and AMD anchoring demand. The result is low utilization risk but continued execution risk around yield, package qualification, and the speed at which new cleanroom capacity converts into shippable HBM.

SK hynix is building a separate $13 billion HBM packaging and testing facility at its Cheongju complex, with construction scheduled to begin April 2026 and completion targeted for end-2027. This is in addition to the 19 trillion won domestic packaging plant disclosed in the base report. At NVIDIA GTC on March 17, SK Group chairman Chey Tae-won stated that the global memory chip shortage is likely to persist until 2030, with industry-wide wafer supply lagging demand by more than 20%. He warned that excessive focus on HBM could lead to shortages in conventional DRAM, affecting smartphones and PCs.

4. Micron — HBM, DRAM, NAND, and Assembly

Micron’s expansion program is the broadest geographically and the most explicit on timing. In FY2Q26 Micron raised FY2026 capex to more than $25 billion and said the majority of the increase was facility and cleanroom capex, with Tongluo in Taiwan the largest driver, followed by U.S. fab projects. Micron also stated that FY2027 capex would step up meaningfully as HBM and DRAM investments continue. That distinction matters because 2026 spending is still heavily pre-output infrastructure spending, while 2027–2028 is when more of that spend starts converting into wafers and packaged bits.

In HBM, Micron is already in commercial ramp. Micron announced high-volume production and volume shipment of its 36GB 12-high HBM4 in Q1 CY26 and said the product was designed for NVIDIA’s Vera Rubin platform. The company also disclosed that 48GB 16-high HBM4 samples had shipped to customers. To support that ramp, Micron and Singapore authorities disclosed an approximately $7 billion advanced packaging investment through the end of the decade and beyond, with operations scheduled to begin in 2026 and meaningful capacity expansion in CY2027. This facility is strategically important because it directly targets the packaging bottleneck that can cap HBM supply even when front-end DRAM wafers are available.

Micron is also adding major NAND capacity in Singapore. The company disclosed an approximately $24 billion, 10-year investment for a new NAND fab inside its existing Singapore manufacturing complex. The project includes a 700,000 square foot cleanroom and is described as Singapore’s 1st double-story wafer fab, with initial wafer output targeted for 2H28. This is one of the clearest and largest NAND capacity additions globally, but it is also a long-dated event. In practical supply terms, it does very little for 2026 and not much for 2027. It matters more as a 2028–2030 NAND supply anchor.

In Taiwan, Micron is converting the former PSMC P5 site in Tongluo into a major DRAM asset. Micron agreed to acquire the site for $1.8 billion in cash, with the existing 300mm cleanroom comprising about 300,000 square feet. In FY2Q26 Micron said meaningful product shipments from the existing Tongluo fab would begin in FY2028 and that construction of a 2nd cleanroom of roughly comparable scale, adding about 270,000 square feet, would begin by the end of FY2026. The timing language is important. The latest disclosure emphasizes meaningful product shipments in FY2028, implying a disciplined, possibly slower-than-initially-modeled ramp tied to node migration, equipment loading, and customer qualification rather than a rapid flood of commodity DRAM bits.

In the U.S., Micron’s roadmap remains enormous but later-dated. The company’s expanded U.S. program totals about $200 billion, including $150 billion for domestic memory manufacturing and $50 billion for R&D, spanning 2 leading-edge Idaho fabs, up to 4 New York fabs, and modernization and expansion in Virginia. Micron’s latest timing indicates initial wafer output from Idaho fab 1 in mid-CY27, with ground preparation for a 2nd Idaho fab already underway and New York site preparation ahead of plan. Federal support is substantial, with a finalized CHIPS award of up to $6.165 billion in direct funding and additional support tied to Virginia expansion. Even so, New York remains a 2030+ event, and Micron has indicated that a full U.S. end-to-end HBM supply chain, including advanced packaging, comes later after enough domestic DRAM wafer capacity exists.

Micron’s India Sanand facility is smaller in strategic importance than its U.S., Taiwan, and Singapore front-end projects, but it still matters to global supply. The company said commercial shipments had started from India’s 1st semiconductor assembly and test facility and that the 1st shipment of India-made memory modules went to Dell Technologies. Micron originally described the project as up to $825 million of direct company investment over 2 phases, supported by a total project cost of up to $2.75 billion with 50% funding from India’s central government and 20% from Gujarat. Phase 1 cleanroom size was disclosed at 500,000 square feet. For 2026 Micron expects tens of millions of chips to be assembled and tested there, rising to hundreds of millions in 2027. This does not change wafer supply, but it improves backend control, module output, and regional delivery capability.

Micron is planning a $9.6 billion HBM facility in Hiroshima, Japan, but initial output is not expected until 2028. Separately, Micron exited the consumer memory market in late 2025, ending its Crucial brand of consumer memory sticks after three decades, triggering what the CEO of custom PC maker Falcon Northwest called a “stampede” to secure inventory and driving consumer memory prices to new highs.

5. China — CXMT, YMTC, Huawei-Led HBM Programs, and Wuhan Xinxin

China’s capacity story is strategically significant but materially less transparent than the Korean, U.S., and Japanese programs. CXMT filed plans for a Shanghai IPO to raise 29.5 billion yuan for production-line construction, technology upgrading, and advanced DRAM R&D, and Reuters reported that the company already operates 3 12-inch DRAM fabs in Beijing and Hefei. Reuters also reported that CXMT is building an HBM back-end packaging facility in Shanghai targeting production by end-2026. In separate reporting, Reuters said CXMT’s initial HBM wafer capacity could be about 30,000 wafers per month and that it aims to start HBM3 mass production in 2026, but those numbers were source-based rather than company-confirmed. The correct analytical treatment is therefore to view China’s HBM emergence as real and strategically important, but still lower-confidence and less transparent than the Korean leaders’ buildouts.

The broader Chinese HBM ecosystem extends beyond CXMT. Reuters reported that Wuhan Xinxin was building a facility capable of producing 3,000 12-inch HBM wafers per month, with construction slated to begin in Feb 2024, and that Huawei had developed HBM samples with domestic partners including Tongfu Microelectronics for client demonstrations. Reuters separately reported that a Huawei-led, government-backed consortium including Fujian Jinhua was seeking to produce HBM by 2026, with at least 2 HBM production lines built and Huawei likely to be the largest buyer. These projects matter because they show China attacking both front-end and back-end bottlenecks. They also remain materially smaller and earlier-stage than the Korean leaders’ programs, and public disclosures do not establish parity with HBM4-class performance, yield, or volume.

YMTC remains primarily a NAND company, but it is beginning to blur into DRAM and HBM-adjacent investment. Reuters reported that YMTC set up a new entity to build a 3rd chip factory in Wuhan with registered capital of 20.7 billion yuan, that it was developing TSV packaging technology used to stack DRAM in HBM, and that it was considering allocating part of the new Wuhan facility to DRAM. Reuters could not establish the new fab’s ultimate monthly capacity or final DRAM share. Reuters also cited a Morgan Stanley note stating that YMTC’s 2 existing Wuhan NAND fabs had 160,000 12-inch wafers per month of capacity by end-2024 and were expected to add 65,000 wafers in 2025. The implication is that YMTC remains China’s largest visible NAND scale-up, but its strategic value is rising because it may become part of a broader domestic AI-memory stack rather than remaining a pure NAND supplier.

6. Taiwan — Nanya, Winbond, and Macronix

Nanya is the most important non-big-3 DRAM greenfield project in Taiwan. Nanya’s groundbreaking materials describe a complex that includes a main fab, R&D center, water recycle center, and a dedicated EUV building, designed to support multiple generations of 10nm-class DRAM from 1A through 1D. Taipei reporting in Mar 2026 said the fab is expected to enter volume production in 1H28 with initial monthly output of 20,000 12-inch wafers and maximum capacity of 45,000 wafers per month, and that 2026 capex would be NT$52 billion to accelerate construction. That places Nanya among the more consequential 2028 conventional DRAM additions outside Samsung, SK Hynix, and Micron.

Nanya’s financing is unusually revealing because it directly ties downstream storage buyers to upstream DRAM security. Reuters reported on Mar 26, 2026 that Nanya raised about $2.5 billion via private placement from SanDisk, Solidigm, Cisco, and Kioxia, with the proceeds earmarked for factory facilities and production equipment for advanced memory manufacturing. SanDisk committed about T$31 billion, while the other 3 investors committed about T$16 billion each. SanDisk and Kioxia also signed long-term DRAM supply agreements with Nanya. This is a notable market-structure development. Buyers and adjacent ecosystem players are no longer waiting for spot markets to clear tightness; they are using equity capital plus offtake agreements to reserve future supply before the fab is online.

Winbond’s relevant expansion is a tooling-and-capacity ramp at Kaohsiung rather than a new greenfield shell. Company materials show 2026 memory capex of about NT$42.1 billion, with roughly 95% allocated to wafer-fab equipment. Separate reporting on the company’s annual disclosures indicated that the Kaohsiung fab had already expanded to about 15,000 wafers per month in 2024. The significance is that Winbond is now in a heavy equipment-loading phase. Exact incremental 2026 volume additions and customer allocations were not publicly itemized in the reviewed materials, so the near-term read is tighter specialty DRAM and flash availability rather than a precisely disclosed unit ramp.

Macronix is executing a smaller but still meaningful specialty NAND and NOR expansion. Taipei reporting in Jan 2026 said the company resumed a NT$22 billion investment plan that adds about 10,000 wafers per month to its 12-inch fab by end-2026, taking capacity from 20,000 to 30,000 wafers per month, or about 50% growth. The project is an expansion of existing facilities rather than a new fab, which shortens the ramp timeline. The company framed the investment as a response to severe shortages in specific NAND and eMMC categories after other suppliers reduced or exited parts of that market. Customer names were not disclosed, but the supply-demand signal is clear: second-tier specialty flash is tight enough to justify restarting a previously delayed capex program.

7. Japan — Kioxia and SanDisk

Kioxia and SanDisk represent the clearest large-scale flash-fab ramp in Japan. Kioxia said operations at Fab2 in Kitakami began on Sep 29, 2025 and that meaningful production output was expected in 1H26 as the ramp proceeded in stages. The fab is designed for 8th-generation BiCS FLASH, including 218-layer 3D flash using CMOS directly bonded to array technology and future nodes. Japan is materially subsidizing the project. Reuters reported that subsidies totaled 242.9 billion yen, including 92.9 billion yen approved earlier and an additional 150 billion yen, against total investment of about 728.8 billion yen. Kioxia’s integrated report showed group capex of 225.6 billion yen in FY2024. No specific customer offtake agreements were disclosed for Fab2 in the reviewed materials, but the project is one of the most important non-Chinese NAND additions now coming online.

7b. SanDisk — NAND Capacity, UltraQLC, HBF, and DRAM Supply Security

SanDisk (SNDK) warrants a dedicated section because it is now a standalone public company with one of the most active capacity and supply-security strategies in the memory space. Following the spin-off from Western Digital, SanDisk controls a pure-play NAND flash business with differentiated positioning across enterprise SSD, consumer storage, and an emerging AI inference memory tier.

Kioxia Manufacturing Extension ($1.17B, 2026–2029). SanDisk extended its joint venture manufacturing partnership with Kioxia, committing $1.17 billion for incremental manufacturing services spanning 2026 through 2029. This secures additional NAND production capacity without the full capital intensity of building new fabs, leveraging the existing Kioxia/SanDisk JV infrastructure in Yokkaichi and Kitakami, Japan.

BiCS8 (218-Layer) 3D NAND. SanDisk successfully ramped production of BiCS8, its 218-layer 3D NAND using CMOS directly bonded to array technology, in 2025. BiCS8 underpins the company’s highest-capacity enterprise products and represents the most advanced production NAND node in SanDisk’s portfolio.

256TB UltraQLC NVMe SSD. SanDisk’s 256TB UltraQLC NVMe SSD, built on BiCS8 QLC NAND, is the highest-capacity enterprise SSD on the market — nearly doubling Micron’s 128TB offerings. The product targets AI data center capacity storage, training data lakes, and KV cache persistence. It is currently qualifying at major hyperscalers.

High Bandwidth Flash (HBF) Standard. On February 25, 2026, SanDisk and SK hynix jointly announced the HBF standard through the Open Compute Project (OCP). HBF creates an entirely new memory tier between HBM and conventional SSDs, specifically designed for AI inference KV-cache workloads. HBF is both complementary to and potentially competitive with NVIDIA’s ICMS/CMX approach. This represents incremental NAND content demand that is not yet reflected in consensus estimates.

Nanya DRAM Equity Investment (~$950M). SanDisk committed approximately T$31 billion (~$950M) as the lead investor in Nanya Technology’s $2.5 billion private placement, alongside Solidigm, Cisco, and Kioxia. SanDisk and Kioxia also signed long-term DRAM supply agreements with Nanya. This is a structural move to secure future DRAM supply — a resource SanDisk needs for SSD controllers and enterprise products but does not manufacture itself.

Data Center Growth. SanDisk raised its internal data center exabyte growth forecast for FY2026 to the upper 60% range, reflecting strong AI-driven demand for enterprise SSDs. The stock is up 132% YTD as of mid-March 2026.

8. HDD — Seagate, Western Digital, and Toshiba

HDD capacity additions are fundamentally different from semiconductor memory expansions. Across the reviewed disclosures, no comparable wave of new greenfield HDD factories was identified. Instead, nearline HDD supply growth is being created through areal-density transitions, head-media advances, and product-platform ramps inside existing manufacturing footprints. For HDD, the relevant capacity questions are therefore qualification pace with hyperscalers, recording-head supply, and the timing of HAMR, MAMR, and ePMR rather than just new buildings.

Seagate is the most advanced in commercial areal-density ramp. Mozaic 4+ is qualified and in production with 2 leading hyperscale cloud customers and supports capacities up to 44TB. Seagate announced a £115 million, 5-year investment in Northern Ireland for next-generation HDD development and photonics-related innovation; the Derry/Londonderry site already produces about 25% of the world’s recording heads. That investment is not a conventional new HDD factory, but it is a meaningful capacity-enabling spend because recording-head supply is one of the binding constraints in HAMR-era scaling. Western Digital’s 40TB UltraSMR ePMR HDD is in qualification with 2 hyperscale customers, with volume production planned for 2H26, while HAMR qualification is underway with 2 hyperscale customers and ramp production is planned in 2027. Toshiba is targeting a 40TB-class 3.5-inch launch in 2027 using 12-disk stacking and MAMR, with its Philippines facility serving as the key large-scale manufacturing base for client, enterprise, and nearline HDDs.

9. Timeline and Ramp Calendar

10. Customer and Offtake Map

11. Pricing, Inventory, and Demand Destruction Context

Current pricing and inventory data reinforce the report's core thesis — supply tightness is structural, not cyclical, and broad commodity relief remains skewed to 2027-2028+.

The pricing data underscores two points. First, the magnitude of price increases is historically extreme — NAND wafers up 246% YoY and PC DRAM up 105-110% QoQ are not normal cyclical recoveries. Second, the demand destruction is already visible in end-market units (PC -10.4%, smartphones -8.4%), but that destruction is a symptom of scarcity, not of weakening demand for compute. AI infrastructure continues to absorb capacity at any price, while consumer electronics absorbs the cost through unit declines and longer replacement cycles.

12. Investment Implications

The buildout described in this note does not support a near-term oversupply framework for DRAM or HBM. Supply tightness is likely to persist through 2026 and into 2027 in the segments most directly tied to AI infrastructure. Broad commodity DRAM and NAND relief is disproportionately weighted toward 2028 and later. The investment conclusions flow directly from the capacity and customer map above.